A MOS device 10, shown in FIG. 1, includes a moderately doped substrate 12 into which two regions 14, 16, called the source and drain, respectively, are diffused. The source 14 and drain 16 are heavily doped with a carrier opposite from that with which the substrate 12 is doped. Adjacent the substrate 12 and between the source 14 and drain 16 is an oxide insulating layer 20. Adjacent the insulating layer 20 is a polycrystaline silicon electrode called a gate 18.
When a potential is applied between the source 14 and drain 16, no current flows unless a potential is also applied between the gate 18 and the substrate terminal 30, which is typically electrically connected to the source 14. As a voltage is applied between the gate 18 and the substrate terminal 30 (and source 14), a region, called a channel 22, is formed which permits conduction between the source 14 and drain 16. This region becomes conductive because the electric field 32 induced in the substrate 12 attracts charged carriers into the channel 22. The amount of conduction is a function of the voltage applied between the gate 18 and the substrate terminal 30 and the voltage applied between the gate 18 and the source 14. Hence, the applied gate voltage may be used to switch the device between conducting and non-conducting states.
The polarity of the carriers, the polarity of the gate potential 28 (which is defined relative to the source 14), and the direction of the electric field 32 depend upon which dopants are used in the substrate 12, the source 14 and the drain 16. If the substrate 12 is p-carrier (hole) doped, then the source 14 and the drain 16 are n-carrier (electron) doped and the device is termed an nMOS device. This device permits current flow when a positive voltage, relative to the source 14 and drain 16, is applied to the gate 18. The electric field vector 32 points away from the gate 18 and electrons move toward the gate-substrate interface forming an n-channel 22. If the substrate 12 is n-carrier (electron) doped, the source 14 and the drain 16 are p-carrier (hole) doped and the device is termed a pMOS device. This device permits current flow when a negative voltage, relative to the source 14 and drain 16, is applied to the gate 18. The electric field vector 32 points toward the gate 18 and holes move toward the gate-substrate interface forming a p-channel 22.
When a low-voltage nMOS high density process device is used to switch a high voltage applied between the source 14 and drain 16, several problems occur, one of which is that the high electric field between the source 14 and the drain 16 may accelerate electrons to such a high energy as to cause the creation of additional electron-hole pairs upon the collision of the energetic electron with the lattice structure of the substrate 12. This process, called impact ionization, affects nMOS devices to a greater degree than pMOS devices because the effective mass of the electrons is less than the effective mass of positively charged carriers. Therefore, the electrons in n-channel devices reach a higher velocity than do holes in p-channel devices. The charged particles move in random directions and may cause further damage to the device by trapping charge in the oxide layer thereby permanently altering the electric field in the vicinity of the channel 22. This damage is similar to that which occurs in the device upon exposure to ionizing radiation.
To avoid these problems, high voltage MOS fabrication techniques may be used in constructing the device. These high voltage MOS fabrication techniques, such as making the oxide layer 20 thicker and increasing the impurity concentration grading in the source 14 and drain 16 region to reduce the electric field density, requires the MOS devices to be larger thereby reducing the device density on a chip.
The present invention permits high density low-voltage MOS devices to be used to switch high voltages without sacrificing device density.